1. Technical Field
Disclosure generally relates to a semiconductor device having a strained semiconductor layer, and a method for manufacturing the semiconductor device.
2. Related Art
The performance of Si-LSI semiconductor elements, especially the performance of Si-MOSFETs, is becoming more and more sophisticated, as the LSI technique is becoming more and more advanced. In recent years, however, the limit of the lithography technique is pointed out from a viewpoint of the processing technology, and the saturation of carrier mobility is pointed out from a viewpoint of element physics. Accordingly, the difficulty in improving the performance of Si-LSI semiconductor elements is becoming greater.
Recently, attention is drawn to a technique by which “strain” is applied to an active layer for device formation, as a technique for increasing the electron mobility and the hole mobility that are a barometer of sophistication of Si-MOSFETs. When strain is applied to an active layer, a change is caused in the band structure of the active layer, and the carrier scattering in the channel is restrained. Accordingly, the carrier (electron, hole) mobility is improved. More specifically, a compound semiconductor crystal layer made of a material having a larger lattice constant than Si, such as a strain-relaxed SiGe compound semiconductor crystal layer (hereinafter referred to simply as the SiGe layer), is formed on a Si substrate. A Si layer is formed on the SiGe layer. As a result, a strained Si layer having strain applied thereto due to the difference in lattice constant is formed. There have been reports that, where such a strained Si layer is used as the channel, improved electron mobility approximately 1.76 times as high as the electron mobility observed in a case where a relaxed Si layer is used as the channel is achieved.
As a technique for forming a strained Si channel on a SOI (Semiconductor On Insulator) structure, there has been a known technique by which a strained Si layer is formed on a SiGe layer formed on a buried oxide layer (BOX layer) on a Si substrate. With this structure, the short channel effect (SCE) in the MOSFET is prevented, and a high-performance semiconductor device is realized.
To obtain even more sophisticated semiconductor elements and achieve miniaturization of the semiconductor elements, a more advanced strain controlling technique is necessary. In recent years, there has been a MOSFET formed on a substrate having strain uniformly applied to the active layer thereof, or a so-called globally-strained substrate. Such a MOSFET has a so-called “biaxially-strained” channel layer to which strain is uniformly applied in the gate length direction (hereinafter also referred to as the Lg direction) parallel to the source/drain direction of the MOSFET, and in the gate width direction (hereinafter also referred to as the Wg direction) perpendicular to the gate length direction. However, it has also been suggested that the characteristics of a semiconductor element can be improved ever with the use of a so-called “uniaxially-strained” channel layer, instead of the “biaxially-strained” channel layer. In the “uniaxially-strained” channel layer, strain is applied in a desired direction, so that the strain in the Lg direction and the strain in the Wg direction become different from each other.
In a semiconductor device of the “hp45 generation” or later that has become smaller with the improvement of the device performance and has a high probability of usage of the above strained semiconductor element, the gate length Lg of the channel in the carrier moving direction is considered to be 50 nm or less. In this case, the size of the active layer forming the source and drain regions and the gate regions for device formation becomes even smaller with the improvement of the integration level. For example, the size of each cell used in a SRAM that is a typical memory is less than 0.1 μm2. More specifically, six transistors are formed in a region as small as 0.1 μm2, and the allowed size of the active layer of each transistor is smaller than 0.5 μm=500 nm in one side length. The active layer of each transistor is formed through mesa isolation of the above-mentioned globally-strained substrate. Therefore, the strain of the active layer might be relaxed due to the pattern size, shape, thickness, or substrate dependence, and systematic studies are required. In other words, to effectively use a strained channel in a state-of-the-art MOSFET, how the strain in the active layer is controlled is an important issue.
Examples of strain measurement methods that are effective in evaluating the characteristics of strained semiconductor elements and are used most widely today include Raman measurement. However, the spot diameter of the laser beam used in the Raman measurement is normally in the neighborhood of half a micron meter (approximately 500 nm in the current experiment level), and is larger than 100 nm or less, which is the spatial resolution required for solving the above-mentioned problem. Also, since the results of Raman measurement are average information in the measured region, it is very difficult to isolate and quantitatively evaluate the strain in a desired direction in a strained semiconductor channel layer formed with the use of the above described globally-strained substrate.
As described above, in a strained semiconductor element, unintended strain relaxation is caused due to miniaturizing and thinning of the channel layer, and the device characteristics improvement by strain might not be achieved. Still, it is not easy to accurately and directly evaluate the strain, and it is difficult to control the strain. Furthermore, controlling the strain applying direction is also important in improving the device characteristics. Still, it is difficult to directly evaluate the strain, and it is even more difficult to control the strain distribution.
The results of the later described studies made by the inventors show that the main cause of strain relaxation greatly depends on the formation of free edges that release the strain, and the relaxation becomes larger more easily if the size of the strained layer is smaller in a case where the strained layer is surrounded by free edges as in a case where the mesa formed on the substrate has a square shape (see K. Usuda, et al., ISTDM06, (2006), for example).